The present invention relates generally to audio, video, and audio/video interconnected systems for home and office use and more specifically to handling resets and topology changes of buses used for interconnection of electronic components.
With the development of consumer electronic audio/video (A/V) equipment, and the advance of digital A/V applications, such as consumer A/V device control and signal routing and home networking, various types of data in various formats can now be transferred among several audio/video control (AV/C) devices via one digital bus system. However, many current systems do not have sufficient bandwidth resources to transfer and display all the different types of data at the same time.
Typical computer systems solve the bandwidth problem by increasing the bandwidth of the system bus to handle all of these forms, types and amount of data. As a result, as users request more types of information such as in multimedia applications, the system bus has become more clogged with information other than information directly utilized and needed by the main processor.
Many computer systems incorporate at least two buses. A first bus, commonly referred to as a memory bus, is typically used for communications between a central processor and a main memory. A second bus, known as a peripheral bus, is used for communications between peripheral devices such as graphics systems, disk drives, or local area networks. To allow data transfers between these two buses, a bus bridge is utilized to xe2x80x9cbridgexe2x80x9d and thereby couple, the two buses together.
One example of a high-speed bus system for interconnecting A/V nodes, configured as a digital interface used to transport commands and data among interconnecting audio/video control (AV/C) devices, is the IEEE 1394 standard serial bus implemented by IEEE Std 1394-1995, Standard For A High Performance Serial Bus, Aug. 30, 1996 (hereinafter xe2x80x9cIEEE 1394 standardxe2x80x9d) and other related 1394 standards.
The IEEE 1394 standard is an international standard for implementing a high-speed serial bus architecture, which supports both asynchronous and isochronous format data transfers. The IEEE 1394 standard defines a bus as a non-cyclic interconnect, consisting of bus bridges and nodes. Within a non-cyclic interconnect, devices may not be connected together so as to create loops. Within the non-cyclic interconnect, each node contains an AV/C device, and bus bridges serve to connect buses of similar or different types.
The primary task of a bridge is to allow data to be transferred on each bus independently without demonstrating performance of the bus, except when traffic crosses the bus bridge to reach the desired destination on the other bus. To perform this function, the bridge is configured to understand and participate in the bus protocol of each of the buses.
Multi-bus systems are known to adequately handle large amounts of information. However, communication between buses and devices on different buses is difficult. Typically, a bus bridge may be used to interface I/O buses to the system""s high-performance processor/memory bus. With such I/O bridges, the CPU may use a 4-byte read and write transaction to initiate DMA transfers. When activated, the DMA of a serial bus node generates split-response read and write transactions which are forwarded to an intermediate system backbone bus that also implements serial bus services.
Depending on the host system design, the host-adapter bridge may have additional features mandated by differences in bus protocols. For example, the host bus may not directly support isochronous data transfers. Also, the host-adapter bridge may enforce security by checking and translating bridge-bound transaction addresses and may often convert uncached I/O transactions into cache-coherent host-bus transaction sequences.
Each time a new device or node is connected or disconnected from an IEEE 1394 standard serial bus, the entire bus is reset and its topology is reconfigured. The IEEE 1394 standard device configuration occurs locally on the bus without the intervention of a host processor. In the reset process, three primary procedures are typically performed; bus initialization, tree identification, and self identification. Within the IEEE 1394 standard, a single node must first be established as the root node during the tree identification process in order for the reconfiguration to occur.
One particular challenge for bus designers concerns handling topology changes on the bus. Topology changes may necessitate new addresses for devices on the bus, recognition of new devices, recognition of the absence of devices, and recognition of differences in pathways to devices. Furthermore, devices may not be completely compatible with the bus, requiring special handling. Additionally, only a finite number of addresses may be available on a bus, so determining how and when to recycle addresses can prove critical to performance of the bus or devices connected to the bus. In particular, use of a timer dedicated to counting to a predetermined address reuse timeout to determine when it is safe to reuse an address on a bus may lead to additional complexity in design of the bus for the purpose of incorporating the new timer.
A method and system for quarantine during bus topology configuration are described. In one embodiment, the invention is a method. The method includes quarantining a set of devices coupled to a bus. The method further includes establishing a topology of the bus. The method may also include receiving a reset signal and quarantining in response to the reset signal. In an alternate embodiment, the invention is a system. The system includes a bus having a reset signal and a plurality of data signals. The system also includes a set of devices, with each device of the set of devices coupled to the bus. The system further includes a controller. The controller having a memory configured to store device identifiers corresponding to the devices of the set of devices. The memory further configured to store quarantine information relating to the devices of the set of devices.